The present invention relates to a method of forming semiconductor transistor devices. In particular, the present invention relates to a method and structure for mixed high voltage/low voltage CMOS devices using controlled gate depletion.
In complementary metal oxide silicon (CMOS) technology, there has been a continuing trend in the semiconductor industry to enhance the speed and density of CMOS integrated circuit devices. Advances in essential fabrication techniques such as photolithography and reactive ion etching (RIE) have contributed to successful device miniaturization and reduction in channel length.
Enhancement of device performance also has been accomplished by efforts to reduce capacitances. However, incorporation of thin silicon oxide gate insulators has led to limitation of voltages that may be high enough to result in gate dielectric wear out or breakdown. Accordingly, in order to facilitate high performance with thin silicon oxide gate dielectrics in specific CMOS device locations where higher voltages are demanded, CMOS device fabrication had to be devised to satisfy both demands. Such customization has been realized by utilizing thicker gate oxide material in the areas demanding higher gate voltages, and using thinner gate oxide layers in the areas where required by performance needs. Disadvantageously, however, processes designed to fabricate gate oxide dielectrics of varying thicknesses either grown or deposited on the same CMOS chip tends to suffer from yield or reliability losses, thus resulting in increases in manufacturing costs. This basically is caused by an intrinsic masking and removal step on one or more of the multiple oxides during the growth or deposition of a second thickness.
Now, according to the present invention, mixed high voltage/low voltage capability in CMOS devices is accomplished by controlling depletion of the gate conductor. Depletion is controlled by leaving a fixed region of the gate conductor intrinsic, or lightly doped, thus separating the heavily doped low resistivity portion of the electrode with an intrinsic region by use of a conducting dopant barrier. The barrier is conductive in nature, but acts as a well controlled diffusion barrier, stopping the xe2x80x9cfastxe2x80x9d diffusion which normally takes place in polysilicon, and eliminating diffusion between the conductors. Device performance can be precisely predicted by carefully controlling gate conductor thickness.